Queueing in High-Performance Packet Switching

Michael G. Hluchyj, Mark J. Karol

Research output: Contribution to journalArticlepeer-review

561 Scopus citations

Abstract

Because of the unscheduled nature of arrivals to a packet switch, two or more packets may arrive on different inputs destined for the same output. The switch architecture may allow one of these packets to pass through to the output, but the others must be queued for later transmission. We study the performance of four different approaches for providing the queueing necessary to smooth fluctuations in packet arrivals to a High-performance packet switch. They are 1) input queueing where a separate buffer is provided at each input to the switch; 2) input smoothing where a frame of b packets is stored at each of the N input lines to the switch and simultaneously launched into a switch fabric of size Nb × Nb; 3) output queueing where packets are queued in a separate first-in first-out (FIFO) buffer located at each output of the switch; and 4) completely shared buffering where all queueing is done at the outputs and all buffers are completely shared among all the output lines. Input queues saturate at an offered load that depends on the service policy and the number of inputs N, but is approximately 0.586 with FIFO buffers when N is large. At the expense of an increase in the switch fabric size and latency, the lost packet rate for input smoothing can be made small by increasing the frame size b. Output queueing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch. However, compared to output queueing, completely shared buffering requires less buffer memory at the expense of an increase in switch fabric size.

Original languageEnglish
Pages (from-to)1587-1597
Number of pages11
JournalIEEE Journal on Selected Areas in Communications
Volume6
Issue number9
DOIs
StatePublished - Dec 1988

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