TY - JOUR
T1 - Performance Analysis of a Growable Architecture for Broadband Packet (ATM) Switching
AU - Karol, Mark J.
AU - Chih-Lin,
PY - 1992/2
Y1 - 1992/2
N2 - A growable architecture for Broadband packet (ATM) switching consisting of a memoryless, self-routing interconnect fabric and modest-size packet switch modules, was recently proposed by Eng, Karol, and Yeh. In this paper, we examine the performance of this architecture. We focus on the cell loss probability, because the architecture attains the best possible delay-throughput performance if the packet switch modules use output queueing. There are two sources of cell loss in the switch. First, cells are dropped if too many simultaneous arrivals are destined to a group of output ports. Second, because a simple, distributed path-assignment controller is used for speed and efficiency, cells are dropped when the controller cannot “schedule” a path through the switch. We compute an upper bound on the cell loss probability for arbitrary patterns of independent cell arrivals, possibly including isochronous circuit connections, and show that both sources of cell loss can be made negligibly small. For example, to guarantee less than 10-9 cell loss probability, this growable architecture requires packet switch modules of dimension 47 × 16, 45 x ×16, 42 × 16, and 39 × 16 for 100, 90, 80, and 70% traffic loads, respectively. The analytic techniques we use to bound the cell loss probabilities are applicable to other output queueing architectures.
AB - A growable architecture for Broadband packet (ATM) switching consisting of a memoryless, self-routing interconnect fabric and modest-size packet switch modules, was recently proposed by Eng, Karol, and Yeh. In this paper, we examine the performance of this architecture. We focus on the cell loss probability, because the architecture attains the best possible delay-throughput performance if the packet switch modules use output queueing. There are two sources of cell loss in the switch. First, cells are dropped if too many simultaneous arrivals are destined to a group of output ports. Second, because a simple, distributed path-assignment controller is used for speed and efficiency, cells are dropped when the controller cannot “schedule” a path through the switch. We compute an upper bound on the cell loss probability for arbitrary patterns of independent cell arrivals, possibly including isochronous circuit connections, and show that both sources of cell loss can be made negligibly small. For example, to guarantee less than 10-9 cell loss probability, this growable architecture requires packet switch modules of dimension 47 × 16, 45 x ×16, 42 × 16, and 39 × 16 for 100, 90, 80, and 70% traffic loads, respectively. The analytic techniques we use to bound the cell loss probabilities are applicable to other output queueing architectures.
UR - http://www.scopus.com/inward/record.url?scp=0026814871&partnerID=8YFLogxK
U2 - 10.1109/26.129205
DO - 10.1109/26.129205
M3 - Article
AN - SCOPUS:0026814871
SN - 0090-6778
VL - 40
SP - 431
EP - 439
JO - IEEE Transactions on Communications
JF - IEEE Transactions on Communications
IS - 2
ER -