Abstract
The authors propose a hybrid packet- and circuit-switched network as a framework for a national broadband (ATM/B-ISDN) (asynchronous transfer mode/broadband-integrated services digital network). Built on the observation that transmission speeds are likely to remain much faster than switching speeds (thus packet switching at peak transmission rates needs to be avoided), the network architecture is a three-tier hierarchy composed of LANs (local area networks), network nodes and DACS (digital access and cross-connect systems). Access to the network is either through direct connection to a DACS or network node, or through the end-user's LAN, which has a gateway to a network node. Each network node is a high-performance ATM packet switch, which accepts input cells at a B-ISDN rate of 150 Mb/s and serves both as LAN-to-LAN interconnect and as a packet concentrator for traffic destined to other network nodes and LANs. To minimize the delay and simplify the implementation of gigabit-per-second packet switching, the network nodes are interconnected by a backbone network of multi-gigabit-per-second fibers and DACS, which provide reconfigurable circuits between network nodes. A congestion-control technique using channel sharing that dramatically reduces the required buffer size is proposed.
Original language | English |
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Pages (from-to) | 515-520 |
Number of pages | 6 |
Journal | Conference Record - International Conference on Communications |
Volume | 2 |
State | Published - 1990 |
Event | IEEE International Conference on Communications - ICC '90 Part 2 (of 4) - Atlanta, GA, USA Duration: 16 Apr 1990 → 19 Apr 1990 |